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1 document # sram128 rev a revised february 2008 p4c1049/p4c1049l high speed 512k x 8 static cmos ram high speed (equal access and cycle times) ? 15/20/25 ns (commercial) ? 20/25/35 ns (industrial) ? 20/25/35/45/55/70 ns (military) low power single 5v10% power supply easy memory expansion using ce ce ce ce ce and oe oe oe oe oe inputs common data i/o three-state outputs functional block diagram pin configurations 1519b fully ttl compatible inputs and outputs advanced cmos technology automatic power down packages ?36-pin soj (400 mil) ?36-pin flatpack ?36-pin lcc (452 mil x 920 mil) features description the p4c1049 is a 4 megabit high-speed cmos static ram organized as 512kx8. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5v10% tolerance power supply. access times as fast as 15 nanoseconds permit greatly enhanced system operating speeds. cmos is utilized to reduce power consumption to a low level. the p4c1049 is a member of a family of pace ram? products offer- ing fast access times. solder-seal flatpack (fs-4), soj (j9, cj2) the p4c1049 device provides asynchronous operation with matching access and cycle times. memory loca- tions are specified on address pins a 0 to a 18 . reading is accomplished by device selection ( ce) and output en- abling ( oe ) while write enable ( we ) remains high. by presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. the input/output pins stay in the high z state when either ce or oe is high or we is low. lcc (l11)
p4c1049 page 2 of 12 document # sram128 rev a p4c1049 maximum ratings (1) symbol parameter value unit v cc power supply pin with ?0.5 to +7 v respect to gnd terminal voltage with ?0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ?55 to +125 c symbol parameter value unit t bias temperature under ?55 to +125 c bias t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma recommended operating temperature and supply voltage i sb standby power supply current (ttl input levels) ce v ih mil. v cc = max, ind./com?l. f = max., outputs open ___ ___ 45 40 15 10 ___ ___ ce v hc mil. v cc = max, ind./com?l. f = 0, outputs open v in v lc or v in v hc standby power supply current (cmos input levels) i sb1 industrial grade(2) ambient temperature gnd v cc 0v 0v 5.0v 10% 5.0v 10% 0v 5.0v 10% ?55c to +125c military symbol c in c out parameter input capacitance output capacitance conditions v in = 0v v out = 0v 8 8 unit pf pf capacitances (4) v cc = 5.0v, t a = 25c, f = 1.0mhz symbol dc electrical characteristics over recommended operating temperature and supply voltage (2) v ih v il v hc v lc i li i lo parameter input high voltage input low voltage cmos input high voltage cmos input low voltage input leakage current test conditions v cc = max. mil. v in = gnd to v cc ind./com?l. v cc = max., mil. ce = v ih , ind./com?l. v out = gnd to v cc min 2.2 ?0.3 (3) v cc ?0.2 ?0.3 (3) ?10 ?5 ?10 ?5 max v cc +0.3 0.8 v cc +0.3 0.2 +10 +5 +10 +5 typ. commercial ?40c to +85c 0c to +70c unit v v v v a a ma ma v ol output low voltage (ttl load) i ol = +8 ma, v cc = min. 0.4 v output high voltage (ttl load) v oh i oh = ?4 ma, v cc = min. 2.4 v output leakage current p4c1049l ___ ___ 40 n/a 10 n/a ___ ___ min 2.2 ?0.3 (3) v cc ?0.2 ?0.3 (3) ?5 n/a ?5 n/a max v cc +0.3 0.8 v cc +0.3 0.2 +5 n/a +5 n/a 0.4 2.4 n/a = not applicable
p4c1049 page 3 of 12 document # sram128 rev a *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il , oe = v ih . i cc symbol parameter temperature range dynamic operating current* commercial industrial military ?15 n/a ?20 ?25 ?35 ?45 ?55 ?70 unit n/a ma ma ma power dissipation characteristics vs. speed n/a n/a n/a n/a 220 n/a 185 190 180 n/a 185 175 n/a data retention characteristics (p4c1049l military temperature only) symbol v dr i ccdr t cdr t r ? parameter v cc for data retention data retention current chip deselect to data retention time operation recovery time test conditons ce v cc ?0.2v, v in v cc ?0.2v or v in 0.2v min 3.0 0 t rc typ.* v cc = 3.0v max v cc = 3.0v unit 23 v ma ns ns *t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested. data retention waveform 165 170 200 195 185 175
p4c1049 page 4 of 12 document # sram128 rev a ac electrical characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) sym. t rc t aa t ac t oh t lz t hz t oe t olz t ohz t pu t pd parameter read cycle time address access time chip enable access time output hold from address change chip enable to output in low z chip disable to output in high z output enable low to low z output enable high to high z chip enable to power up time chip disable to power down time output enable low to data valid min max min max min max min max min max min max min max -20 -25 -35 -45 -55 -70 -15 unit 15 3 3 0 0 15 15 8 7 7 15 20 3 3 0 0 20 20 9 9 9 20 25 3 3 0 0 25 25 11 10 10 25 35 3 3 0 0 35 35 15 15 15 35 45 3 3 0 0 45 45 20 20 20 45 55 3 3 0 0 55 55 25 25 25 55 70 3 3 0 0 70 70 30 30 30 70 ns ns ns ns ns ns ns ns ns ns ns timing waveform of read cycle no. 1 ( oe oe oe oe oe controlled) (5)
p4c1049 page 5 of 12 document # sram128 rev a timing waveform of read cycle no. 2 (address controlled) (5,6) timing waveform of read cycle no. 3 ( ce ce ce ce ce controlled) (5,7) notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?2.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. we is high for read cycle. 6. ce is low and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce transition low. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specified in figure 1. this parameter is sampled and not 100% tested. 9. read cycle time is measured from the last valid address to the first transitioning address.
p4c1049 page 6 of 12 document # sram128 rev a -35 ac characteristics?write cycle (v cc = 5v 10%, all temperature ranges) (2) sym. t wc t cw t as t wp t ah t dw t dh parameter write cycle time chip enable time to end of write address set-up time write pulse width address hold time date hold time data valid to end of write min max min max min max min max min max min max min max -20 -25 -45 -55 -70 -15 unit 15 12 0 20 14 0 25 0 16 0 35 0 22 0 45 0 25 0 55 0 30 0 70 0 35 0 12 0 9 14 0 11 18 16 0 13 22 20 0 15 30 25 0 20 35 35 0 25 40 40 0 30 ns ns ns ns ns ns ns ns t aw address valid to end of write 12 14 00 write enable to output in high z t wz 8 101115182530ns output active from end of write t ow 3335555ns timing waveform of write cycle no. 1 ( we we we we we controlled) (10,11)
p4c1049 page 7 of 12 document # sram128 rev a notes: 10. ce and we must be low for write cycle. 11. oe is low for this write cycle to show t wz and t ow . 12. if ce goes high simultaneously with we high, the output remains in a high impedance state 13. write cycle time is measured from the last valid address to the first transitioning address. timing waveform of write cycle no. 2 ( ce ce ce ce ce controlled) (10)
p4c1049 page 8 of 12 document # sram128 rev a input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 ac test conditions figure 1. output load figure 2. thevenin equivalent * including scope and test fixture. note: because of the ultra-high speed of the p4c1049, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73v (thevenin voltage) at the comparator input, and a 116 resistor must be used in series with d out to match 166 (thevenin resistance). write active read truth table mode standby standby d out disabled standby power i/o we we we we we oe oe oe oe oe ce ce ce ce ce high z high z d out high z x x h h l x x h l x h l l l standby active active high z x
p4c1049 page 9 of 12 document # sram128 rev a ordering information
p4c1049 page 10 of 12 document # sram128 rev a pkg # # pins symbol min max a 0.130 0.145 a1 0.082 - b 0.015 0.020 c 0.007 0.013 d 0.920 0.930 e e 0.435 0.445 e1 0.395 0.405 e2 q 0.045 0.055 j9 36 0.050 bsc 0.370 bsc solder seal flatpack soj small outline ic package pkg # # pins symbol min max a 0.089 0.125 b 0.015 0.019 c 0.003 0.007 d 0.910 0.930 e 0.505 0.515 e1 - 0.530 e2 0.385 0.395 e3 0.055 0.065 e l 0.300 0.350 q 0.015 0.038 s-0.045 m - 0.0015 n fs-4 36 0.050 bsc 36
p4c1049 page 11 of 12 document # sram128 rev a pkg # # pins symbol min max a 0.080 0.100 a1 0.054 0.066 b 0.022 0.028 d 0.910 0.930 d1 0.840 0.860 e 0.445 0.460 e l l2 0.115 0.135 p - 0.006 r .050 bsc .100 typ .009 typ l11 36 rectangular leadless chip carrier ceramic soj small outline ic package pkg # # pins symbol min max a 0.120 0.165 b1 b2 b3 0.025 0.045 d 0.816 0.838 e 0.419 0.431 e2 0.360 0.380 e e1 0.430 0.454 cj2 36 0.050 bsc 0.030r typ 0.020 ref
p4c1049 page 12 of 12 document # sram128 rev a revisions document number : sram128 document title : p4c1049 / p4c1049l high speed 512k x 8 static cmos ram rev. issue date orig. of change description of change or oct-05 jdb new data sheet a jan-08 jdb added cj2 ceramic soj package

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